Signal processing circuit

ABSTRACT

A circuit for applying a predetermined algorithm to an input signal, has an input for receiving the input signal, a signal processing device for processing the input signal in accordance with the predetermined algorithm, and a device for outputting the processed signal. The signal processing device incorporates distributed bit-serial logic circuits to implement the predetermined algorithm.

This invention relates to a circuit for applying a predeterminedalgorithm to an input signal.

Such a circuit may be, for example, a circuit for encoding or decodingspeech samples using ADPCM (Adaptive Differential Pulse CodeModulation).

ADPCM (Adaptive Differential Pulse Code Modulation) is a digital signalprocessing algorithm designed to reduce the bandwidth of Pulse CodeModulated Speech samples. CCITT recommendation G.721 (Melbourne 1988)describes the algorithm in detail as it pertains to the conversion of 64kb/s μ-law or A-law PCM encoded speech to and from a 32 kb/s compressedformat. ANSI recommendation T1-303, and CCITT rec G.726 are similardocuments with extensions to 40 k/s and 24 kb/s and 16 kb/s bit rates.The actual implementation of an ADPCM algorithm in a real time speechprocessing application may take various different forms ranging from acomputer program, instruction code on a commercially available DSP chip,ASIC logic chip, or a custom integrated circuit.

This invention is concerned with implementation in the form of a customchip. In the prior art, implementation has been achieved in this form byemploying microprocessor technology using a high speed clock to run acircuit consisting of a multiplexed ALU (arithmetic logic unit) circuit,state machine, or micro-coded instruction based processor. The algorithmhas to be coded as a stored program, and the power consumption involvedis very substantial when fetching instructions, decoding and executingthe instructions, which requires large data buses to be pulled up anddown, continually charging and discharging CMOS transistor gates.Furthermore a lot of instructions are required to execute the program.

Analysis of prior art ADPCM devices available reveals that powerconsumption has not been optimized. In practice, the minimum powerrequirements are in the order of several hundred milliwatts.

Particularly in Pair Gain (twisted pair line quadrupling) applicationsand Cordless Digital telephones (e.g. Personal Handy Phone handsets andbase-stations), power consumption is becoming a major preoccupation ofcircuit designers.

Pair Gain is a method of increasing the number of subscribers that maysimultaneously use a single analog twisted pair telephone line forindependent two-way conversations. A/D and D/A converters (CODEC'S) areused to digitize the speech channels into 64 kb/s A-law or μ-law PCM,after which one or more ADPCM devices are used to compress the 64 kb/sstreams to 32 kb/s. These 32 kb/s channels are then merged into a singleISDN Ubus transceiver device to transmit the digitized signals as one144 kb/s (2B+D) base-band modem signal onto a single twisted pair coppercable. At the distant end of the cable, similar devices are used toreconvert the signals back to analog form to interface with separateanalog telephones.

Pair Gain equipment is used in locations where the cost of installationof copper pair cable for additional telephone lines proves to beprohibitively expensive (or more expensive than the Pair Gainequipment).

Because it is desirable that the Pair Gain equipment circuitry be linepowered (i.e. powered by DC on the line itself), it is necessary thatthe power consumption of the devices used be minimized. There is arelationship between maximum line length possible with the Pair Gainequipment and the power consumption of the circuit. This means that thecurrent consumption of the ADPCM device directly affects performanceparameters of the Pair Gain product.

Cordless digital telephones that conform to the CT2 (Cordless Telephone2) specification or other specifications use a codec to convert signalsfrom analog to digital and back, as well as ADPCM compression to 32 kb/sto reduce the bandwidth of the digital signal before transmission. Sincethe telephone set must be battery operated, the power consumption of thecomponents will directly affect the number of hours of usage before thebattery must be recharged. This means that the current consumption ofthe ADPCM device directly affects performance parameters of a cordlesstelephone product.

U.S. Pat. No. 4,858,163 describes a serial arithmetic processor which isarranged to perform complex arithmetic functions of the ADPCM algorithm.This patent (U.S. Pat. No. 4,858,163) relates to a common means serialarithmetic processor (SAP) for efficiently performing certain selectedcomplex arithmetic functions in the ADPCM algorithm, intended for usealong with a micro-coded processor to implement the main body of ADPCMalgorithm. The micro-coded processor has a 16 bit bus connected to aRAM, an ALU core, and a 1024×29 bit ROM. The Serial Arithmetic Processoris attached to this micro-coded processor via the multiplexed 16 bitbus.

The objects of this prior art patent are to provide an SAP comprising acommon means to efficiently perform complex arithmetic functions such asLOG, ANTILOG, FLOATING POINT MULTIPLICATION and SIGNED MAGMULTIPLICATION. The advantage of this design is stated to be areplacement for arithmetic functions which are burdensome to implementusing the available instruction sets of presently available digitalsignal processing chips. This appears to be the only advantage, and theactual reasons for choosing serial logic circuitry are not welldocumented.

U.S. Pat. No. 4,791,590 discloses the use of bit-serial logic circuitsfor carrying fast Fourier Transform operations. It does not, however,disclose an architecture suitable for low-power ADPCM applications, suchas are found in cordless telephones.

British patent no. 2,218,548 discloses a special purpose Digital SignalProcessor for implementing ADPCM in a cordless phone. However, thisprocessor uses mostly 16-bit parallel logic, which results inunnecessarily power consumption.

An object of the invention is to provide a circuit capable ofimplementing the ADPCM algorithm with reduced power consumption.

According to the present invention there is provided a circuit forapplying an adaptive differential pulse code modulation compressionalgorithm to an input signal, comprising an input for receiving saidinput signal, signal processing means for processing said input signalin accordance with said algorithm, wherein the signal processing meanscomprises distributed bit-serial logic circuits and includes an adaptivepredictor having a parallel array of bit-serial floating pointmultipliers whose outputs are connected to respective adders, where theyare summed serially to produce an output.

This arrangement offers considerable advantages both in terms of thereduction in logic circuitry and power consumption. Bit serial logiccircuitry has a substantially lower power consumption than parallellogic circuitry.

The present invention has a significant advantage over the prior art,particularly U.S. Pat. No. 4,858,163, in that a micro-program processorarchitecture is not used. In accordance with the invention, allarithmetic functionality of the ADPCM algorithm is implemented as aparallel array of bit serial logic such that each arithmetic function isseparate and not multiplexed (i.e. there are no common means forexecution of different arithmetic functions). The ADPCM algorithm isactually hard wired into the connection of separate bit serial circuits.Such an implementation has a more optimal way of performing arithmeticcalculations from the point-of-view of low power consumption. The burdenof fetching decoding and executing stored instructions is avoided.

An example of why a stored micro-code implementation is less efficientwill be described. Assume that a functional step in a DSP algorithmrequires a single bit to be set or cleared in a 16 bit binary registervariable, which is stored in ram. The micro-coded processor has to readthis entire variable (all 16 bits) out of the RAM, move it to an ALU(arithmetic logic unit), then set or clear the appropriate bit usinglogical instructions, and then move the result back to RAM. This wholesequence of operations has the overhead of instruction fetch/decode/andexecution from memory, as well as activity on the internal data bus foreach of the 16 bits of the entire variable, as well as one or more ALUoperations. In contrast, the corresponding logic designed specificallyto implement this operation is as simple as directly setting or clearinga single flip-flop in a register. This therefore corresponds to adrastic reduction in total power drawn for this simple operation (whenCMOS logic gates are used).

The overall implementation of a DSP algorithm using bit serial logicmust therefore in general be a lower power solution than that of thesame implemented in a stored micro-programmable DSP even with some ofthe more burdensome operations designed into a SAP as in the abovepatent.

In accordance with the present invention the QUANTIZER, INVERSEQUANTIZER, FORMAT CONVERSION, DIFF signal computation, TONE/TRANSITIONdetector, SCALE FACTOR, SPEED CONTROL filters are all implemented as bitserial logic circuits in serial hardware as opposed to software. TheFMULT operation which is the floating point multiply operation insidethe ADAPTIVE PREDICTOR is probably the most arithmetically complexoperation in the ADPCM algorithm. The present invention does not use aparallel adder, and instead sums partial products together through anarray of six serial adders to produce the final product in bit serialform which is shifted into shift register. In the CCITT FMULTdefinition, the product of the multiplication must be shifted accordingto the result of the addition of exponents. Most data transfers are doneserially, consequently data shift operations are accomplished simply bydelaying a serial stream of data. This data shift is implemented bydelaying the data in a shift register depending upon the resultgenerated by an exponent adder, 5 bit loadable down counter, anddecode/control logic.

Arithmetic operations such as additions, subtractions, 2's complementinversions, multiplications etc., require large amounts of logic gatesif implemented in parallel. If instead, the operations are doneserially, bit by bit beginning with the least significant bits, then therequired amount of logic reduces significantly.

Preferably said predetermined algorithm is an ADPCMcompression/decompression algorithm.

The implementation of the circuit is in the form of a Custom IntegratedCircuit using standard cell 2 μm CMOS silicon technology. Theimplementation follows the CCITT/ANSI recommendations for 32 kb/s and 24kb/s ADPCM in terms of arithmetic processing; however, the use ofdistributed bit-serial logic implementation have resulted insubstantially lower power consumption than the prior art, namely in theorder of 10-12 mwatts for one encoder and one decoder using a 5 v powersupply, or 3-5 mWatts using a 3 V power supply.

The invention will now be described in more detail, by way of exampleonly, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of an ADPCM encoder operating according toCCITT standard G.726;

FIG. 2 is a block diagram of an ADPCM decoder operating according toCCITT standard G.726;

FIG. 3 is a circuit of a bit serial adder in accordance with oneembodiment of the invention;

FIG. 4 is a circuit of a bit serial subtracter in accordance with oneembodiment of the invention;

FIG. 5 is a block diagram of an adaptive predictor as defined by CCITTspecifications;

FIG. 6 is an ADDC implementation circuit;

FIG. 7 is a floating point multiplier unit (FMULT);

FIG. 8 is a block diagram of an FMULT floating point converter;

FIG. 9 shows a Prediction Coefficient Update Circuit (UPB, XOR, TRIGB);

FIG. 10 is a floating point conversion circuit (FLOATA);

FIG. 11 is a timing chart for the circuit of FIG. 10; and

FIG. 12 shows a second floating point converter circuit (FLOATB).

FIG. 1 shows a block diagram of a circuit implementing the ADPCMalgorithm as defined in CCITT specifications. In FIG. 1, the 64 kb/sADPCM input stream s(k) is input to a ADPCM format converter 1 connectedto difference signal unit 2. The difference signal d(k) is fed toadaptive quantizer 3, which produces an output signal I(k) that is inputto inverse adaptive quantizer 4 producing an output d_(q) (k) input toadaptive predictor 5. The outputs of inverse adaptive quantizer 4 andadaptive predictor 5 are respectively applied as inputs to reconstructedsignal calculator 6 whose output s_(r) (k) is applied to adaptivepredictor 5.

The output of inverse adaptive quantizer d.sub.(k) is also applied totone transition detector 7, along with an output of adaptive predictor5, and the output of tone and transition detector 7 is applied toadaptive speed control unit 8, in turn connected to quantizer scalefactor and adaptation unit 9. The ADPCM output appears at the input toinverse adaptive quantizer 4.

The encoder circuit FIG. 1 is specified in document CCITT G.726, towhich the reader is referred. Throughout this specification theprocessing variables will be identified using the same terminology as isemployed in this document.

FIG. 2 shows a decoder circuit which receives at its input an ADPCMsignal and provides at its output a PCM signal s_(d) (k). The individualcomponent of the circuits of FIG. 2 are generally similar to those ofFIG. 1, and like reference numbers are employed where appropriate. Theoutput of the reconstructed signal calculator 6 is applied to an outputPCM format conversion circuit 10, which in turn is connected to asynchronous coding adjustment circuit 11. This is circuit is alsodescribed in detail in CCITT document G.726. In FIGS. 1 and 2, theillustrated blocks 1 to 9 and 4 to 11 respectively constitute signalprocessing means for applying an ADPCM compression algorithm to an inputsignal. The circuit of FIG. 1 compresses the signal and the circuit ofFIG. 2 decompresses it using the same basic algorithm. When implementedin parallel logic, the circuits shown in FIGS. 1 and 2 constitute priorart

Referring now to FIG. 3, the bit serial adder comprises an exclusive ORgate 20 having inputs A and B and an output connected to one input of anexclusive OR gate 21. The inputs of AND gate 22 are also connected torespective inputs A and B, and the inputs of AND gate 23 arerespectively connected to output of exclusive OR gate 20 and a secondinput of exclusive OR gate 21, which in turn is connected to the Q⁻output of bistable flip flop 24. The outputs of AND gates 22 areconnected through NOR gate 25 to the D input of flip flop 24.

Arithmetic operations such as additions, subtractions, 2's complementinversions, multiplications etc., require large amounts of logic gatesif implemented in parallel. If instead, the operations are doneserially, bit by bit beginning with the least significant bits, then therequired amount of logic reduces significantly.

The following example illustrates an example of serial addition withreference to FIG. 3. If for example two operands of length 16 bits areto be added together, then the operands are shifted in serially LSB(Least Significant Bit) first into inputs A and B, with resulting serialsum at output S.

The XOR gates 20, 21 perform the single bit 2's complement addition, andthe carry bit generated by the AND/OR combination is latched and usedduring the next single bit addition. Initialization of the latched carrybit C is done using the signal PRESET before the first addition of theLSB'S.

A simple change in this circuit, wherein inverter 26 is added to the Binput of exclusive OR gate 20, produces a 2's complement subtracter asshown in FIG. 4. The PRESET on the flip-flop has changed from a SET to aRESET function, which effectively causes the first carry bit C to be aONE, and the B input bits are all complemented resulting in a 2'scomplement addition of (A plus the one's complement of B plus ONE).

This methodology can be easily extended to implement any arithmetic orlogical function, including multiplication. Delays or register storageare implemented using shift registers, which are clocked only whenneeded.

Turning now to FIG. 5, this illustrates an adaptive predictor unit 5 ofFIGS. 1 and 2 implemented using serial logic in accordance with theinvention. In FIG. 5, the adaptive predictor comprises a parallel arrayof six FMULT bit serial logic units 30 connected to respective bitserial adders 31, each FMULT unit 30 producing serial bit streams WB1 toWB6. Floating point converter 36, shown in more detail in FIG. 10,provides an input to the array. A second parallel array of two floatingpoint multipliers 30 receives an input from floating point converter 37,shown in more detail in FIG. 12, and outputs signals WA1, WA2. These bitstreams are summed in the adders 31, which produce outputs SE and SEZ asrequired by the ACCUM operation defined in the CCITT specifications.

The first six FMULT units 30, producing outputs WB1 to WB6, areconnected to combined XOR, UPB and TRIGB predictor units 32 (shown inmore detail in FIG. 9), whereas the remaining FMULT units 30 producingoutputs WA1, WA2 are connected to predictor units 33.

The circuit of FIG. 5 generally operates in accordance with the CCITTG.726 ADPCM.

Turning now to FIG. 6, this shows a bits serial logic circuit inaccordance with the invention, which implements ADDC operation (block 34in FIG. 5) as well as PK delays (inputs to predictors 33 in FIG. 5) asdefined in CCITT G.726.

In FIG. 6, serial streams SEZ and DQ are summed in serial adder 40 toform a resulting signal DQSEZ which is latched into flip flops 41 at theappropriate time using clock signal EN1, which is generated elsewhere inthe chip. The outputs of the flip flops 41 form signals PK0, PK1, andPK2 respectively. RS latch 42 generates an output SIGPK by firstclearing SR latch output low using reset signal START which occursbefore serial adder 40 begins its calculation. Each bit of the resultingsignal DQSEZ is gated with clock CK1 using AND gate 43 to deglitch thebit signals to form a set signal to SR latch 42. In the event that anyof the bits of DQSEZ are logic high, SR latch 42 will be set highcausing SIGPK to become logic high.

FIG. 7 shows in detail a floating point multiplier block 30 (FMULT)implemented as a bit serial logic circuit. In FIG. 7, DQn signals shiftserially through Shift Register 50 to implement to the DQ0 to DQ6 delayline. Shift Register 50 is tapped off in parallel to provide thecomponents of the DQn (Quantized Difference) signal to the floatingpoint multiplier. These components are the six bit wide DQnMANT, thefour bit wide DQnEXP, and the single bit DQnS, and are available to beused by the floating point multiplier when Shift Register 50 is static,i.e. when SCLK is not active.

The other input to the floating point multiplier is from 13 bit linearmagnitude BnMAG and sign bit BnS. BnMAG is shifted serially intofloating point converter 51 and converted into six bit wide BMANT signaland four bit wide BnEXP signal. BnMANT and DQnMANT are gated togetherthrough AND gate array 52 and serial adder array 53 to form the resultWBnMANT, which is a 12 bit serial bit stream representing the mantissaof the product.

To understand how this multiplication works, it must be realized thatthe six bit bus DQnMANT is a collection of static signals representing amultiplicand, but the six bit bus BnMANT is not a static bus and isactually a collection of shifted serial bit streams generated by thefloating point converter 51. The following shows the serial bit streamsas defined on each signal of BnMANT, shifted LSB first.

    ______________________________________                                                      MSB      LSB                                                    ______________________________________                                        BnMANT (0)      0 0 0 0 0 0                                                                              1 b.sub.4 b.sub.3 b.sub.2 b.sub.1 b.sub.0          BnMANT (1)      0 0 0 0 0 1                                                                              b.sub.4 b.sub.3 b.sub.2 b.sub.1 b.sub.0 0          BnMANT (2)      0 0 0 0 1 b.sub.4                                                                        b.sub.3 b.sub.2 b.sub.1 b.sub.0 0 0                BnMANT (3)      0 0 0 1 b.sub.4 b.sub.3                                                                  b.sub.2 b.sub.1 b.sub.0 0 0 0                      BnMANT (4)      0 0 1 b.sub.4 b.sub.3 b.sub.2                                                            b.sub.1 b.sub.0 0 0 0 0                            BnMANT (5)      0 1 b.sub.4 b.sub.3 b.sub.2 b.sub.1                                                      b.sub.0 0 0 0 0 0                                  ______________________________________                                    

The above can also be written as BnMANT(n) <<n, i.e. a bit shift to theright of n bits. These serial streams are then gated through AND gates52 and summed serially in summers 53 to produce the sum of partialproducts. Additionally a value of 48 is added to the result as perrequirement in CCITT G.726FMULT description.

The result WBnMANT is shifted into shift register 54 clocked by logiccircuit 55, the clock from which is enabled by strobe EN1, which isgenerated elsewhere in the chip. Only the eight most significant bits ofWBnMANT are kept, the four LSB'S are discarded, thus shift register 54is an 8 bit register. The value held in shift register 54 is held for aperiod of time and then shifted out at an appropriate time to generate16 bit serial signal WBn. AND gate 56 is used to remove unwanted bitsfrom WBnMAG which is then converted from a magnitude format to a 2'scomplement format by MUX circuit 57 to generate WBn in serial fashion.MUX 57 is used to select either the magnitude WBnMAG or the 2'scomplement of WBnMAG generated by serial complement circuit 58. MUX 57is controlled by XOR gate 59, the inputs of which are the sign bits ofthe multiplier BnS and multiplicand DQnS.

The period of time that register 54 is held static is determined byexponent adder 60, 5 bit loadable down counter 61, logic circuit 62, andlogic circuit 55, the operation of which will be explained next.Exponent adder 60 adds BnEXP to DQnEXP and produces a 5 bit resultWBnEXP. WBnEXP is used as the preset value loaded into a 5 bit downcounter 61. The three most significant bits of this down counter aredecoded by logic circuit 55 to generate signal CKEN. If a value greaterthan or equal to 11 is loaded into the counter then the clock to thedown counter becomes enabled by CKEN. When the counter reaches a countof 11 then CKEN will stop the clock to the counter freezing the count at11. Signal EN2SCOMP is also generated and conditioned by circuit 55 toproduce the clock WCLK used to clock shift register 54. The delay beforeWCLK is started is dependent upon the value of WBnEXP produced by thesummation of exponents 60, and the number of clock cycles before thedown counter reaches a count of 11. This implements the requiredshifting to scale WBnMAG as per CCITT G.726.

The Floating Point Converter block 51 is shown in FIG. 8. A 6 bit shiftregister 70 is first cleared by the START signal, which also initializesthrough OR gate 71, the loadable shift register 72, to the binary value"100000", shift register 73 of all zeros, as well as counter 74 to acount of 13. Serial input signal BnMAG is shifted into least significantbit first using a clock signal COUNTCLK. When a logic "1" bit isencountered in the BnMAG stream, three things happen, firstly the leastsignificant 5 bits of shift register 70 are loaded into loadable shiftregister 72 along with a logic "1" bit in the most significant bitposition, secondly output shift register 73 is cleared to all zeros(actually a redundant operation), and thirdly 4 bit down counter 74 ispreset to a count of 13. The loadable shift register 72 now contains theprevious 5 bits in the BnMAG stream before the logic "1" was detected,along with a "1" in the most significant bit position. Since a multiplenumber of occurrences of "1" may occur in the BnMAG input stream, thisload process is repeated until the last occurrence of a "1" is found.Every subsequent "0" in the BnMAG stream will have no effect upon thecircuit except that the down counter 74 will decrement by 1 count. Afterthe last bit of BnMAG has been clocked into shift register 70, COUNTCLKis disabled and SHIFTCLK becomes active. The value left in the downcounter 74 is the desired exponent value BnEXP, which is output from thecircuit in parallel fashion. Loadable shift register 72, is shiftedserially through shift register 73 to produce the shifted bit streamsshown in the table above.

The Predictor Coefficient Update (UPB) block is shown in FIG. 9. Thiscircuit performs an adaptive coefficient update for the predictorfilter. The outputs of this circuit provide the multiplier input to anFMULT floating point multiplier circuit shown in FIG. 7. The 16 bit 2'scomplement representation of the filter coefficient Bn is stored inshift register 80. During adaptation, clock signal SHIFTCLK becomesactive shifting the register contents through serial adders 81 and 82.Signal Bn>>8 is a signal tapped from the 8th flip-flop of the shiftregister and represents the value of Bn shifted right by 8 bits. Latch83 allows signal Bn>>8 to pass through transparently until the mostsignificant bit (the sign bit) of Bn>>8 is present at the output oflatch 83, the latch enable EN3 (from elsewhere in the chip) is thenchanged to logic "O" causing the sign bit of Bn>>8 to become latched soas to extend the sign bit through subsequent bit periods so as to effecta 2's complement sign bit extension. AND gate 84 clears serial bitstream BnP to all zeroes when input signal TR is asserted to logic "1"to implement the TRIGB definition as per CCITT G.726. XOR gate 85implements the XOR operation on input sign bits DQS and DQnS to generatesignal "Un" as per CCITT definition. Logic gates 86 along with inputstrobe pulses STRB1, STRB2, and STRB3, generate signal UGBn which is oneof 3 possible 2's complement serial codes (+80hex, -80hex, or 0).

Simultaneously with coefficient update previously described, signalsBnMAG and BnS are produced and transmitted to the FMULT circuit. Thesign bit of Bn (labeled as Bn>>15) is tapped-off the shift register atthe rightmost bit position. This signal is latched at the appropriatetime by signal EN3 to latch 86 to hold the sign bit BnS. Bn>>2 is alsotapped-off the shift register two positions from the left most end ofthe register and passed through serial circuit 87 which converts the 2'scomplement representation of Bn>>2 to signed magnitude representationBnMAG. The operation of this conversion circuit is similar to the one inthe FMULT circuit.

The FLOATA block shown in FIG. 10 converts a 15 bit signed magnitudeDQMAG signal along with sign bit DQS to floating point representationfor use by the FMULT floating point multipliers. The inputs and outputsof this circuit are serial format least significant bit first.

Shift register 90 is first cleared by the START signal, which alsoinitializes through OR gate 91, the loadable shift register 92, and 4bit down counter 93. Serial input signal DQMAG is shifted into shiftregister 90 least significant bit first using clock signal CLK1. When alogic "1" bit is encountered in the DQMAG stream, two things happen,firstly the least significant 5 bits of shift register 90 are loadedinto loadable shift register 92 along with a logic "1" bit in the mostsignificant bit position, and secondly the 4 bit down counter 93 ispreset to a count of 14.

The loadable shift register 92 will now contain the previous 5 bits inthe DQMAG stream before the logic "1" was detected, along with a "1" inthe most significant bit position. Since a multiple number ofoccurrences of "1" may occur in the DQMAG input stream, this loadprocess is repeated until the last occurrence of a "1" is found. Everysubsequent "0" in the DQMAG stream will have no effect upon the circuitexcept that the down counter 93 will decrement by 1 count. After thelast bit of DQMAG has been clocked into shift register 90, CLK2 becomesactive (CLK1 remains active) and 4 bit down counter 93 stops countingand switches its function to that of a shift register; the change infunction being indicated by control input COUNT/SHIFT generatedelsewhere on the chip. The value left in the down counter is the desiredexponent value DQEXP, which along with input sign bit DQS becomesserially connected to shift register 92 and the final result DQO isshifted out serially using CLK1 and CLK2. The input and output signalsare shown in FIG. 11.

The FLOATB block shown in FIG. 12 converts a 16 bit 2's complement SRsignal to floating point representation for use by the FMULT floatingpoint multipliers. The inputs and outputs of this circuit are serialformat least significant bit first. The operation of this circuit isidentical to that of the FLOATA circuit previously described, with theexception of the inclusion of a 2's complement to signed magnitudeconversion circuit 100, 101, 102.

The circuits described show how distributed serial bit logic circuitscan be applied to implement the ADPCM algorithm as defined in the CCITTspecifications with economy of power and logic circuitry. It will beapparent to a person skilled in the art that the invention will findmany other applications in the field of digital signal processing.

The circuits are particularly advantageous because of their very lowpower consumption, which is extremely valuable in small portable batterypowered devices, such as telephone handsets.

I claim:
 1. In a circuit for applying an adaptive differential pulsecode modulation compression algorithm to an input signal, comprising aninput for receiving said input signal, signal processing means forprocessing said input signal in accordance with said algorithm, theimprovement wherein said signal processing means is implemented usingdistributed bit-serial logic circuits and includes an adaptive predictorhaving a parallel array of bit-serial floating point multipliers whoseoutputs are connected to respective bit serial adders, where they aresummed serially to produce an output.
 2. A circuit as claimed in claim1, wherein said bit serial adders each comprise an array of logic gatesand a flip-flop.
 3. A circuit as claime in claim 1, implemented in theform of a single integrated chip with low power consumption.
 4. Acircuit as claimed in claim 1, wherein said floating point multiplierscomprise a floating point converter, and a serial adder array forproducing a sum of partial products of the multiplicands, one of themultiplicands being represented by a collection of static signals andthe other of the multiplicands being represented by a collection ofshifted serial bit streams generated by a floating point converter.
 5. Acircuit as claimed in claim 4, wherein said floating point multipliersfurther comprise an array of AND gates connected between said floatingpoint multiplier and said serial adder array, whereby said serial bitstreams are gated together through said array of AND gates prior tobeing applied to said serial adder array.
 6. A circuit as claimed inclaim 5, wherein the mantissa of said multiplicands form the inputs tosaid array of AND gates.
 7. A circuit as claimed in claim 6, furthercomprising an exponent adder for adding the exponents of saidmultiplicands, a down counter connected to the output of said exponentadder, and further serial logic circuitry for combining the output ofthe down counter with the product of the mantissa to form the resultingproduct.
 8. A circuit as claimed in claim 7, wherein the output of saidfurther serial logic circuitry is used to derive a clock signal for ashift register receiving at its input the product of said mantissa.
 9. Acircuit as claimed in claim 8, wherein said further serial logiccircuitry comprises logic gates and bistable flip-flops.
 10. A circuitas claimed in claim 4, wherein said floating point converter comprises ashift register receiving at its input one of the multiplicands,additional shift registers for deriving the mantissa thereof, and a downcounter for deriving the exponent thereof.
 11. A circuit as claimed inclaim 1, further comprising a floating point converter for deriving aDQO signal applied to said floating point multipliers and comprising ashift registers and a down counter.
 12. A circuit as claimed in claim 1,further comprising predictor coefficient update circuits are connectedto the inputs of said floating point multipliers, said predictorcoefficient update circuits comprising a shift register storing a 2'scomplement of a filter coefficient, and logic circuitry receivingsignals controlling said shift register to generate filter coefficients.13. A circuit as claimed in claim 1, wherein said bit serial adderscomprise a first AND gate connected to a pair of serial inputs, a firstexclusive OR gate connected to said pair of inputs, a DQ flip flophaving a Qbar output connected to a first input of a second AND gate anda first input of a second exclusive OR gate, the output of said firstexclusive OR gate being connected to a second input of the second ANDgate and a second input of said second exclusive OR gate, and theoutputs of said first and second AND gates being connected through a NORgate to the D input of said DQ flip-flop.